Systematic Variation of Transistor Characteristics from High Volume Wafer Fabrication

This student team worked to leverage their engineering and data science skill sets to tackle a real world manufacturing data set. The initial stage of the project focused on data engineering, analysis, and method building. Upon assessment of data correlations, this student team worked to narrow scope and dig deeper into a portion of semiconductor fabrication process to identify root cause. DRAM CMOS devices exhibit systematic variation in threshold voltage resulting from the hundreds of process steps used to fabricate them. Micron suspected that some process variation [tool-to-tool, wafer-to-wafer] was directly correlated. This student team worked to identify the process steps, whose variability had the greatest influence on wafer level median NFET and PFET Vt. Under this problem statement, this student team worked to identify influential process steps and attempted to build a physical root cause assessment. Additional data or process details were provided on a need base as the project progressed. This project presented students with the opportunity to utilize their engineering and data science training on a real world problem set. The student team also had the opportunity to network with Micron, with the intent of helping students to explore careers in the growing area of domestic semiconductor manufacturing and R&D.

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